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16 - bit, 500 ksps pulsar adc in msop data sheet ad7 686 features 16- bit resolution with no missing codes throughput: 500 ksps inl: 0.6 lsb typical, 2 lsb maximum (0.003% of fsr) s inad : 92.5 db at 20 khz thd: ?110 db at 20 khz pseudo differential analog input range 0 v to v ref with v ref up to vdd no pipeline delay single - supply 5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface proprietary serial interface : spi - /qspi? - /microwire? - /dsp - compatible daisy - chain multiple adcs and busy indicator power dissipation 3.75 w at 5 v/100 sps 3.75 mw at 5 v/100 ksps s tandby current: 1 na 10- lead msop (msop - 8 size) and 3 mm 3 mm , 10 - lead lfcsp (sot - 23 size) pin - for - pin - compatible with 10 - lead msop/pulsar ? adcs applications battery - powered equipment data acquisitions instrumentation medical instruments process control s code inl (lsb) 2.0 1.5 1.0 0.5 0 ? 0.5 ? 1.0 ? 1.5 ? 2.0 0 16384 32768 49152 65535 02969-007 positive inl = +0.52lsb negative inl = ? 0.38lsb figure 1 . integral nonlinearity vs. code 1. protected by u.s. patent 6,703,961. functional block dia gram ad7686 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v t o vdd 3- or 4-wire inter f ace (spi, dais y chain, cs) 0.5v t o 5v 5v 0 t o vref 02969-002 figure 2. table 1 . msop, lfcsp /sot - 23 14 - /16 - /18- bit pulsar adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18 - bit true ad7691 ad7690 ad7982 ada4941 differential ad7982 ada4941 16 - bit true ad7684 ad7687 ad7688 ada4941 differential ad7693 ada4841 16 - bit pseudo ad7680 ad7685 ad7686 ad7980 ada4941 differential ad7683 ad7694 14 - bit pseudo differential ad7940 ad7942 ad7946 ada4941 general description the ad7686 1 is a 16 - bit, charge redistribution, successive approximation, analog - to - digital converter (adc) that operates from a single 5 v power supply , vdd. it contains a low power, high speed, 16 - bit sampling adc with no missing codes, an internal conver sion clock, and a versatile serial interface port. the part also contains a low noise, wide bandwidth, short aperture delay track - and - hold circuit. on the cnv rising edge, the ad7686 samples an a nalog input in+ between 0 v to ref with respect to a ground sense in?. the reference voltage, ref, is applied externally and can be set up to the supply voltage. power dissipation scales linearly with throughput. the spi - compatible serial interface also fe atures the ability , using the sdi input, to daisy - chain several adcs on a single, 3 - wire bus or provides an optional busy indicator. this device is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate supply vio. the ad7686 is housed in a 10 - lead msop or a 10 - lead lfcsp with operatio n specified from ?40c to +85c. rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwi se under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2005 C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
ad7686* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7686 evaluation kit ? precision adc pmod compatible boards documentation application notes ? an-931: understanding pulsar adc support circuitry ? an-932: power supply sequencing data sheet ? ad7686: 16-bit, 500 ksps pulsar? adc in msop/qfn data sheet product highlight ? [no title found] product highlight ? 8- to 18-bit sar adcs ... from the leader in high performance analog ? lowest-power 16-bit adc optimizes portable designs (eeproductcenter, 10/4/2006) user guides ? ug-340: evaluation board for the 10-lead family 14-/16-/ 18-bit pulsar adcs ? ug-682: 6-lead sot-23 adc driver for the 8-/10-lead family of 14-/16-/18-bit pulsar adc evaluation boards software and systems requirements ? ad7686 fmc-sdp interposer & evaluation board / xilinx kc705 reference design ? bemicro fpga project for ad7686 with nios driver tools and simulations ? ad7685 ibis models reference materials technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc design resources ? ad7686 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7686 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7686 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 circuit information .................................................................... 12 converter operation .................................................................. 12 typical connection diagram .................................................... 13 analog input ............................................................................... 14 driver amplifier choice ........................................................... 15 voltage reference input ............................................................ 15 power supply ............................................................................... 15 supplying the adc from the reference .................................. 16 digital interface .......................................................................... 16 cs mode 3 - wire, no busy indicator .................................... 17 cs mode 3 - wire with busy indicator ..................................... 18 cs mode 4 - wire, no busy indicator ....................................... 19 cs mode 4 - wire with busy indicator ..................................... 20 chain mode, no busy indicator .............................................. 21 chain mode with busy indicator ............................................. 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating the performance of the ad7686 ............................ 23 true 16 - bit isolated application example .............................. 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 26 revision history 8 /14 rev. b to rev. c deleted qfn .................................................................. throughout change to feature s section ............................................................. 1 added patent note , note 1 .............................................................. 1 added epad notation to figure 6 and table 6 ............................ 7 changes to evaluating the perf ormance of the ad7686 section .............................................................................................. 23 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 26 3 /07 rev. a to rev. b changes to features and t able 1 ..................................................... 1 changes to table 3 ............................................................................ 4 moved figure 3 and figure 4 to page ............................................. 5 changes to figure 13 and figure 15 ............................................. 10 changes to figure 26 ...................................................................... 13 changes to table 8 .......................................................................... 15 changes to figure 31 ...................................................................... 16 changes to figure 42 ...................................................................... 21 changes to figure 44 ...................................................................... 22 updated outline dimensions ....................................................... 25 ch anges to ordering guide .......................................................... 26 4/06 rev. 0 to rev. a updated format .................................................................. universal updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 26 4/05 revision 0: initial version rev. c | page 2 of 28
data sheet ad7686 specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = C 40c to +85c, unless otherwise noted. table 2. b grade c grade parameter test conditions /comments min typ max min typ max unit resolution 16 16 b its analog input voltage range in+ ? in? 0 v ref 0 v ref v absolute input voltage in+ ?0.1 v dd + 0.1 ?0.1 v dd + 0.1 v i n? ?0.1 + 0.1 ?0.1 + 0.1 v f in = 200 khz 65 65 db a cquisition phase 1 1 na a n a log input cmrr l e a kag e c u rrent at 25 c input impedance s ee the analog input section see the analog input section accuracy no missing codes 16 16 b its differential linearity error ?1 0.7 ?1 0.5 +1.5 lsb 1 integral linear ity error ?3 1 +3 ?2 0.6 +2 lsb 1 transition noise ref = vdd = 5 v 0. 5 0. 45 ls b 1 gain error 2 , t min to t max 2 8 2 6 ls b 1 gain error temperature drift 0.3 0.3 ppm /c offset error 2 , t min to t max 0.1 1.6 0.1 1.6 mv offset temperature drift 0.3 0.3 ppm /c power supply sensitivity vdd = 5 v 5% 0.05 0.05 ls b 1 through put conversion rate 0 500 0 500 ks ps transient response full - scale step 400 400 ns ac accuracy signal -to - noise ratio f in = 20 khz, v ref = 5 v 89 92 91 92. 7 db 3 f in = 20 khz, v ref = 2.5 v 87. 5 88 db 2 spurious - free dynamic range f in = 20 khz ? 106 ? 110 db 2 total harmonic distortion f in = 20 khz ?106 ?110 db 2 signal -to - (noise + distortion) f in = 20 khz, v ref = 5 v 89 92 91 92. 5 db 2 f in = 20 khz, v ref = 5 v, ?60 db input 32 33. 5 db 2 intermodulation distortion 4 ? 110 ? 115 db 2 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 76.3 v. 2 see the terminology section. these specifications do include full temperature range variation , but do not include the error contribution from the external reference. 3 all specifications in db are referred to a full - scale input fs r . tested with an input signal at 0.5 db below full scale, unless otherwise specified. 4 f in 1 = 21.4 khz, f in2 = 18.9 khz , each tone at ?7 db below full scale . rev. c | page 3 of 28
ad7686 data sheet vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = C 40c to +85c, unless otherwise noted. table 3 . parameter test conditions /comments min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 500 ksps, ref = 5 v 100 a sampling dynamics ?3 db input bandwidth 9 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il C 0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits straight binary pipel ine delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4.5 5.5 v vio specified performance 2.3 vdd + 0.3 v vio ra nge 1.8 vdd + 0.3 v standby current 1 , 2 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 5 v, 100 sps throughput 3.75 w vdd = 5 v, 100 ksps throughput 3.75 4.3 mw vdd = 5 v, 500 ksps throughput 15 21.5 mw temperature range 3 spec ified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 conta ct sales for extended temperature range. rev. c | page 4 of 28
data sheet ad7686 timing specification s ?40c to +85c, vdd = 4.5 v to 5.5 v, vio = 2.3 v to 5.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. see figure 3 and figure 4 for load conditions. table 4 . parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2 s cnv pulse w idth ( cs mode ) t cnvh 10 ns sck period ( cs mode ) t sck 15 ns sck period (chain mode) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode ) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode ) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode ) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode ) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode ) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 3 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode wit h busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns 500 a i o l 500 a i oh 1.4v t o sdo c l 50pf 02969-003 figure 3 . load circuit for digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t del a y t del a y 02969-004 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. figure 4 . voltage levels for timing rev. c | page 5 of 28
ad7686 data sheet absolute maximum rat i ngs table 5 . parameter rating analog inputs in+ 1 , in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v t o vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 200c/w (msop - 10) jc thermal impedance 44c/w (msop - 10) lead temperature jedec j - std -20 1 see the analog input section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution rev. c | page 6 of 28
data sheet ad7686 pin configurations a nd function descript ions 02969-005 ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7686 t o p view (not to scale) figure 5 . 10 - lead msop pin configuration 02969-006 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9 sdi 8 sck 7 sdo 6 cnv ad7686 top view (not to scale) notes 1. exposed pad. the exposed pad must be connected to ground. this connection is not required to meet electrical performances. figure 6 . 10 - lead lfcsp pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. this pin should be dec oupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai analog input. it is referred to in ?. the voltage range, that is, the difference between in+ and in?, is 0 v to v ref . 4 in? ai analog input ground sense. it is connected to the analog ground plane or to a remote sense ground. 5 gnd p power supply ground. 6 cnv di convert input. this inpu t has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode, chain, or cs . in cs mode, it enables the sdo pin when low. in chain mode, the data should be read wh en cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows : chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or m ore adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial out put signals when low. if sdi or cnv is low when the conversion is complete d , the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). epad n/a exposed pad. the exposed pad must be connected to ground. this connection is not required to meet electrical performances. 1 ai = analog input, di = digital input, do = digital output, and p = p ower . rev. c | page 7 of 28
ad7686 data sheet terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negat ive full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 25). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specifi ed in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from tha t point. gain error the last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transi tion from the ideal level after the offset is adjusted out. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in db. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal -to - (noise + distortion) , s inad sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in db. aperture delay it is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function i s applied. rev. c | page 8 of 28
data sheet ad7686 t ypical performance c haracteristics code in l (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0 16384 32768 49152 65535 02969-007 positive in l = +0.52lsb neg a tive in l = ?0.38lsb figure 7 . integral nonlinearity vs. code 02969-008 counts 250000 200000 150000 100000 50000 0 code in hex 802b 802c 802d 802e 8026 8027 8028 8029 802 a 0 0 26 0 0 202719 30770 27583 22 vdd = ref = 5v figure 8 . histogram of a dc input at the code center 02969-009 frequenc y (khz) 120 0 20 40 60 80 100 200 220 240 140 160 180 amplitude (db of ful l scale) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 ?180 8192 point fft vdd = ref = 5v f s = 500ksps f in = 19.99khz snr = 92.8db thd = ?108.7db second harmonic = ? 1 10.1db third harmonic = ? 1 19.2db figure 9 . fft plot code dn l (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0 16384 32768 49152 65535 02969-010 positive dn l = +0.35lsb neg a tive dn l = ?0.36lsb figure 10 . differential nonlinearity vs. code 02969-0 1 1 counts 160000 140000 120000 100000 60000 80000 20000 40000 0 code in hex 802b 8024 8026 8025 8027 8028 8029 802 a 0 0 1703 0 0 124164 133575 1678 vdd = ref = 5v figure 11 . histogram of a dc input at the code transition 02969-012 input leve l (db) 0 ?10 ?8 ?6 ?4 ?2 thd (db) ?120 ?105 ?108 ? 11 1 ? 1 14 ? 1 17 snr (db) 95 94 93 92 91 90 snr thd figure 12 . snr and thd vs. input level rev. c | page 9 of 28
ad7686 data sheet 02969-013 reference vo lt age (v) 5.5 2.3 2.7 3.5 4.3 5.1 3.1 3.9 4.7 snr, sinad (db) 100 95 85 90 70 snr enob enob (bits) 17.0 15.0 16.0 14.0 13.0 sinad figure 13 . snr, sinad , and enob vs. reference voltage 02969-014 temper a ture ( c ) 125 ?55 ?35 ?15 5 25 45 65 85 105 snr (db) 100 95 90 85 80 vref = 5v figure 14 . snr vs. temperature 02969-015 frequenc y (khz) 200 0 50 100 150 sinad (db) 100 95 85 90 80 75 70 vref = 5 v , ?10db vref = 5 v , ?1db figure 15 . sinad vs. frequency 02969-016 reference vo lt age (v) 5.5 2.3 2.7 3.5 4.3 5.1 3.1 3.9 4.7 thd, sfdr (db) ?90 ?95 ?100 ?105 ? 1 10 ? 1 15 ?120 ?125 ?130 thd sfdr figure 16 . thd, sfdr vs. reference voltage 02969-017 temper a ture ( c ) 125 ?55 ?35 ?15 5 25 45 65 85 105 thd (db) ?90 ?100 ? 1 10 ?120 ?130 vref = 5v figure 17 . thd vs. temperature 02969-018 frequenc y (khz) 200 0 50 100 150 thd (db) ?60 ?70 ?90 ?80 ?100 ?1 10 ?120 vref = 5 v , ?10db vref = 5 v , ?1db figure 18 . thd vs. frequency rev. c | page 10 of 28
data sheet ad7686 supp l y (v) oper a ting currents ( a) 1000 750 500 250 0 4.50 4.75 5.00 5.25 5.50 02969-019 vio vdd f s = 100ksps figure 19 . operating currents vs. supply temper a ture ( c) power-down currents (na) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 02969-020 vdd + vio figure 20 . power - down currents vs. temperature temper a ture ( c) oper a ting currents ( a) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 02969-021 vio vdd = 5v f s = 100ksps figure 21 . operating currents vs. temperature 02969-022 temper a ture ( c) 125 ?55 ?35 5 45 105 85 ?15 25 65 offse t , gain error (lsb) 4 3 2 1 ?0 ?1 ?2 ?3 ?4 offset error gain error figure 22 . offset and gain error vs. temperature 02969-023 sdo ca p acitive load (pf) 120 0 20 40 60 80 100 t dsdo del a y (ns) 25 20 15 10 5 0 vdd = 5 v , 85c vdd = 5 v , 25c figure 23. t dsdo delay vs. capacitance load and supply rev. c | page 11 of 28
ad7686 data sheet theory of o peration sw+ msb 16,384c in+ lsb com p contro l logic switches contro l bus y output code cnv ref gnd in? 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c 02969-024 figure 24 . adc simplified schematic circuit information the ad7686 is a fast, low power, single - supply, precise 16 - bit adc using a successive approximation architecture. the ad7686 is capable of converting 500,000 samples per second (500 ksps) and powers down between conversions. for example, when operating at 100 sps, the device consumes 3.75 w typically, which is ideal for battery - powered applications. the ad7686 provides the user with on - chip , track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for mult iple , multiplexed channel applications. the ad7686 is specified from 4.5 v to 5.5 v and can be interfaced to any of the 1.8 v to 5 v digital logic family. it is housed in a 10- lead msop or a tiny 10- lead lfcsp that combines space savings and allows flexible configurations. this device is pin - for - pin - compatible with the ad7685 , ad768 7 , and ad7688 . converter operation the ad7686 is a successive approximation adc based on a charge redistribution dac. figure 24 shows a simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to two comparator inputs. during the acquisition phase, terminals of th e array tied to the comparator input ar e connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complet e and the cnv input goes high, a conversion phase initiate s . when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in?, captured at the end of the acquisition phase, is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input var ies by binary weighted voltage steps (v ref /2, v ref /4 . . . v ref /65536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the a cquisition phase and the control logic generates the adc output code and a busy signal indicator. because the ad7686 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. rev. c | page 12 of 28
data sheet ad7686 transfer functions the ideal transfer characteristic for the ad7686 is shown in figure 25 and table 7 . 000...000 000...001 000...010 11 1...101 11 1... 1 10 11 1... 11 1 adc code (straight bina r y) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 02969-025 figure 25 . adc ideal transfer function table 7 . output codes and ideal input voltages description analog input v ref 5 v digital output code headecimal fsr C 1 lsb 4.999924 v fff f 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale C 1 lsb 2.499924 v 7fff C fsr + 1 lsb 76.3 v 0001 C fsr 0 v 0000 2 tpical connection d iagram figure 26 shows an example of the r ecommended connection diagram for the ad7686 when multiple supplies are available. 1 thi s is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). ad7686 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire inter f ace 5 100nf 100nf 5v 10 f 2 7v 7v ?2v 1.8v t o vdd ref 1 0 t o vref 33 ? 2.7nf 3 4 02969-026 1 see the vo lt age reference input section for reference selection. 2 c ref is usual l y a 10 f ceramic ca p aci t or (x5r). 3 see driver amplifier choice section. 4 optiona l fi l ter. see analog input section. 5 see digi t a l inter f ace section for most convenient inter f ace mode. figure 26 . typical application diagram with multiple sup plies rev. c | page 13 of 28
ad7686 data sheet analog input figure 27 shows an equivalent circuit of the input structure of the ad7686 . the two diodes, d1 and d2, provide esd protection for the analog inputs in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v because this causes these diodes to begin to forward - bias and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a cas e, an input buffer with a short - circuit current limitation can be used to protect the part. c in r in d1 d2 c pin in+ or in? gnd vdd 02969-027 figure 27 . equivalent analog input circuit the analog input structur e allows the sampling of the differential signal between in+ and in?. by using this differential input, small signals common to both inputs are rejected, as shown in figure 28 , which represents the typical cmrr ov er frequency. for instance, by using in? to sense a remote signal ground, ground potential differences between the sensor and the local adc ground are eliminated. 02969-028 frequenc y (khz) 10000 1 10 100 1000 cmrr (db) 80 70 60 50 40 vdd = 5v figure 28 . analog input cmrr vs. frequency during the acquisitio n phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 ? and is a lum ped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in a nd c in make a 1 - pole, low - pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7686 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency, as shown in figure 29. 02969-030 frequenc y (khz) 100 0 25 50 75 thd (db) ?80 ?85 ?90 ?95 ?100 ?105 ? 1 10 r s = 33 ? r s = 50 ? r s = 100 ? r s = 250 ? figure 29 . thd vs. analog input frequency and source resistance rev. c | page 14 of 28
data sheet ad7686 driver amplifier cho ice although the ad7686 is easy to drive, the driver amplifier should meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transit ion noise performance of the ad7686 . note that the ad7686 has a noise much lower than most of the other 16 - bit adcs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. the noise coming from the amplifier is filtered by the ad7686 analog input circuit 1 - pole, low - pass filter made b y r in and c in or by the external filter, if one is used. because the typical noise of the ad7686 is 37 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 37 37 20log n 3db loss ne f snr ee f 3db e dd f e ad e ff fee f e fe f e ed n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the ad7686 . figure 18 shows the thd vs. frequency that the d river should exceed. ? for multichannel multiplexed applications, the driver amplifier and the ad7686 analog input circuit must settle a full - scale step onto the capacitor array at a 16 - bit level (0.0015%). in the data sheet for the amplifier, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16 - bit level and should be verified prior to driver selection. table 8 . recommended driver amplifiers amplifier typical application ada4841 -x very low noise and low power ad8605 , ad8615 5 v single - supply, low power ad8655 5 v single - supply, low power op184 low power, low noise, and low frequency ad8021 very low noise and high frequency ad8022 very low noise and high frequency ad8519 small, low power and low frequency ad8031 high frequency and low power voltage reference in put the ad768 6 voltage reference input, ref, has a dynamic input impedance and should, therefore, be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source, such as a reference buffer using the ad8031 or the ad8605 , a 10 f (x5r, 0805 size) ce ramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performanc e using a low temperature drift adr43x reference. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. regardles s, there is no need for an additional lower value ceramic decoupling capacitor, such as 100 nf, between the ref and gnd pins. power supply the ad7686 is specified at 4.5 v to 5.5 v. the device uses two power supply pins: a core supply vdd and a digital input/ output interface supply vio. vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd can be tied together. the ad7686 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 30 , which represents psrr over frequency. 02969-031 frequenc y (khz) 10000 1 1000 10 100 psrr (db) 1 10 100 90 80 70 60 50 40 30 vdd = 5v figure 30 . psrr vs. frequency rev. c | page 15 of 28
ad7686 data sheet the ad7686 powers down automatically at the end of each conversion phase and, the refore, the power scales linearly with the sampling rate, as shown in figure 31 . this makes the part ideal for low sampling rates (even a few hz) and low battery - powered applications. sampling r a te (sps) oper a ting currents ( a) 1000 100 10000 10 1 0.1 0.01 0.001 10 100 1000 10000 100000 1000000 02969-032 vio vdd = 5v figure 31 . operating current s vs. sampling rate supplying the adc fr om the reference for simplified applications, the ad7686 , with its low operating current, can be supplied directly using the re ference circuit shown in figure 32 . the reference line can be driven by either: ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr43x . ? a reference buffer, such as the ad8031 , which can also filter the system power supply, as shown in figure 32. ad8031 ad7686 vio ref vdd 10 f 1 f 10 ? 10k ? 5v 5v 5v 1 f 1 02969-033 1 optiona l reference buffer and fi l ter. figu re 32 . example of application circuit digital interface though the ad7686 has a reduced number of pins, it offers flexibility in its serial interface modes. the ad7686 , when in cs mode, is compatible with spi, qspi, digital hosts, and dsps, such as black fin ? adsp - bf53x or adsp - 219x . this interface can use either 3 - wire or 4 - wire. a 3 - wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4 - w ire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the ad7686 , when in chain mode, provides a daisy - chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level wh en the cnv rising edge occurs. the cs mode is selected if sdi is high , and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is always selected. in either mode, the ad7686 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigge r the data reading. otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. the busy indicator feature is enabled as follows: ? in cs mode, if cnv or sdi is low when the adc conversion ends ( see figure 36 and figure 40 ). ? in chain mode, if sck is high during the cnv rising edge ( see figure 44). rev. c | page 16 of 28
data sheet ad7686 cs mode 3 - wire, no busy indica tor this mode is most often used when a single ad7686 is connected to an spi - compatible digital host. the connection diagram is shown in figure 33, and the corresponding timing is provided in figure 34. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sd o to high impedance. once a conversion is initiated, it continues to completion irrespective of the state of cnv. for instance, it could be useful to bring cnv low to select other spi devices, such as analog multiplexers. however, cnv must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid generating the busy signal indicator. when the conversion is complete, the ad7686 enters the acquisit ion phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital h ost using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the 16th sck falling edge , or when cnv goes high, whichever occurs first, sdo returns to high impedance. cnv sck sdo sdi d at a in clk convert vio digi t a l host ad7686 02969-034 figure 33 . cs mode 3 - wire, no busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 14 15 16 t sck t sck l t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 02969-035 figure 34 . cs mode 3 - wire, no busy indicator serial interface timing (sdi high) rev. c | page 17 of 28
ad7686 data sheet cs mode 3 - wire w ith busy indicator this mode is generally used when a single ad7686 is connected to an spi - compatible digital host having an interrupt input. the connection diagram is shown in figure 35, and the correspond - ing timing is provided in figure 36. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forc es sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion, irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers. however, cnv must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull - up on th e sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7686 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 17th sck falling edge or when cnv goes high, whichever occurs first, sdo returns to high impedance. if multiple ad7686 s are selected at the same time , the sdo output pin handles this connection without damage or induced latch - up. m eanwhile, it is recommended to keep this connection as short as possible to limit extra power dissipation. d at a in irq clk convert vio digi t a l host 02969-036 47k ? cnv sck sdo sdi vio ad7686 figure 35 . cs mod e 3 - wire with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sck l t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc t cnvh t acq acquisition sdi = 1 02969-037 figure 36 . cs mode 3 - wire with busy indicator serial interface timing (sdi high) rev. c | page 18 of 28
data sheet ad7686 cs mode 4 - wire, no busy indica tor this mode is generally used when multiple ad7686 s are connected to an spi - compatible digital host. a connection diagram example using two ad7686 devices is shown in figure 37, and the corresponding timing is given in figure 38. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi could be use d to select other spi devices, such as analog multiplexers. but sdi must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is comple te, the ad7686 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are t hen clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate , provided it has an acceptable hold time. aft er the 16th sck falling edge or when sdi goes high, whichever occurs first, sdo returns to high impedance and another ad7686 can be read. dat a in clk cs1 convert cs2 digi t al host 02969-038 cnv sck sdo sdi ad7686 cnv sck sdo sdi ad7686 figure 37 . cs mode 4 - wire, no busy indicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 30 31 32 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sck l t sckh d0 d15 d14 17 18 16 sdi(cs2) 02969-039 figure 38 . cs mode 4 - wire, no busy indicator serial interface timing rev. c | page 19 of 28
ad7686 data sheet cs mode 4 - wire with busy indic ator this mode is usually used when a single ad7686 is connected to an spi - compatible digital host, which has an interrupt input, and when it is desired to keep cnv, which is used to sample the analog input, ind ependent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 39, and the correspo nding timing is provided in figure 40. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before th e minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when conversion is complete, sdo goes from high impedance to low. with a pull - up on the sdo line, this transition can be us ed as an interrupt signal to initiate the data readback controlled by the digital host. the ad7686 then enters the acquisition phase and powers down. the data bits are then clocked out, msb firs t, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate , provided it has an acceptable hold time. after the op tional 17th sck falling edge or sdi going high, whichever occurs first, the sdo returns to high impedance. d at a in irq clk convert cs1 vio digi t a l host 02969-040 47k ? cnv sck sdo sdi ad7686 figure 39 . cs mode 4 - wire with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sck l t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 02969-041 figure 40 . cs mode 4 - wire with busy indicator serial interface timing rev. c | page 20 of 28
data sheet ad7686 chain mode, no busy indicator this mode can be used to daisy - chain multiple ad7686 s on a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a conne ction diagram example using two ad7686 s is shown in figure 41, and the corresponding timing is given in figur e 42. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readb ack. when the conversion is complete, the msb is output onto sdo , and the ad7686 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are then clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read back the n adcs . the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7 686 s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate can be reduced due to the total readback time. for instance, with a 3 ns digital host setup time and 3 v interface, up to four ad7686 s running at a conversion rate of 360 ksps can be daisy - chained on a 3 - wire port. clk convert d at a in digi t a l host 02969-042 cnv sck sdo sdi ad7686 b cnv sck sdo sdi ad7686 a figure 41 . chain mode, no busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 30 31 32 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sck l t sckh d a 0 17 18 16 sdi a = 0 sdo b d b 15 d b 14 d b 13 d a 1 d b 1 d b 0 d a 15 d a 14 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 02969-043 figure 42 . chai n mode, no busy indicator serial interface timing rev. c | page 21 of 28
ad7686 data sheet chain mode with busy indicator this mode can be used to daisy - chain multiple ad7686 s on a 3 - wire serial interface while providing a busy indi cator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connecti on diagram example using three ad7686 s is shown in figure 43, and the corresponding timing is given in figure 44. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent dat a readback. when all adcs in the chain have completed their conversions, the near - end adc (adc c in figure 43 ) sdo is driven high. this transition on sdo can be used as a busy indicator to trigger the data readb ack controlled by the digital host. the ad7686 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are then clocked out, msb first, by subsequen t sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7686 s in the chain, provided the digital host has an accept able hold time. for instance, with a 3 ns digital host setup time and 3 v interface, up to four ad7686 s running at a conversion rate of 360 ksps can be daisy chained to a single 3 - wire port. clk convert dat a in irq digi t al host 02969-044 cnv sck sdo sdi ad7686 c cnv sck sdo sdi ad7686 a cnv sck sdo sdi ad7686 b figure 43 . chain mode with busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 35 47 48 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 4 15 t sck t sckh t sck l d a 0 17 34 16 sdo b = sdi c d b 15 d b 14 d b 13 d a 1 d b 1 d b 0 d a 15 d a 14 49 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 15 d c 14 d c 13 d a 1 d a 0 d c 1 d c 0 d a 14 19 31 32 18 33 d b 1 d b 0 d a 15 d b 15 d b 14 t dsdosdi t ssckcnv t hsckcnv 02969-045 d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi figure 44 . chain mode with busy indicator serial interface timing rev. c | page 22 of 28
data sheet ad7686 application hints layout the printed circuit board (pcb) that houses the ad7686 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7686 , with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because doing so couples noise onto the die, unless a ground plane under the ad7686 is used as a shield. fast switching signals, such as cnv or clocks, should never run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground pl ane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the devices. the ad7686 voltage reference inpu t ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the ref and gnd pins and connecting it with wide, low impedance traces. finally, the ad7686 power supplies vdd and vio should be decoupled with ceramic capacitors (typically 100 nf) placed close to the ad7686 and connected using short and wide traces. this provides low impedance paths and reduces the effect of glitches on the power supply lines. examples of layouts that follow these rules are s hown in figure 45 and figure 46. evaluating the p erformance of the ad7686 other recommended layouts for the ad7686 are outlined in the documentation of the e va l - ad7686sbz evaluation board . the e va l - ad7686sbz evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - sdp - cb1z . 02969-046 figure 45 . example of layout of the ad7686 (top layer) 02969-047 figure 46 . example of layout of the ad7686 (bottom layer) rev. c | page 23 of 28
ad7686 data sheet true 16 - bit isolated applica tion example in applications where high accuracy and isolation are required, such as power monitoring, motor control, and some medical equipment, the circuit shown in figure 47 , using the ad7686 and the adum1402c digital isolator, provides a compact and high performance so lution. multiple ad7686 devices are daisy - chained to reduce the number of signals to isolate. note that the sckout, which is a readback of the ad7686 clock, has a very short skew with the data signal. this skew is the channel - to - channel matching propagation delay of the digital isolator (t pskcd ). this allows running the serial interface at the maximum speed of the digital isolator (45 mbps for the adum1402c ), which would have been otherwise limited by the cascade of the propagation delays of the digital isolator. for instance, four ad7686 devices running at 330 ksps can be chained together. the complete analog chain runs on a single 5 v supply using the adr391 low dropout reference voltage and the rail - to - rai l cmos ad8618 amplifier while offering true bipolar input range. in? gnd ref vdd vio sdo v dd1 , v e1 gnd 1 v dd2 , v e2 gnd 2 sck cnv sdi ad7686 1/4 ad8618 5v 1k ? 2v ref 10v input 5v ref 5v 5v 10 f 100nf 100nf in? gnd ref vdd vio sdo sck cnv sdi ad7686 1/4 ad8618 5v 1k ? 2v ref 10v input 5v ref 5v 10 f 100nf in? gnd ref vdd vio sdo sck cnv sdi ad7686 1/4 ad8618 5v 1k ? 2v ref 10v input 5v ref 5v 10 f 100nf in? in+ in+ in+ in+ gnd ref vdd vio sdo sck cnv sdi ad7686 1/4 ad8618 5v 1k ? 4k ? 4k ? 4k ? 4k ? 2v ref 5v 5v 1k ? 1k ? 1k ? 100nf 10 pf 5v ref 2v ref 4k ? 10v input 5v ref 5v 10 f 100nf v ia v ib v oc v od v oa v ob v ic v id 2.7v t o 5v 100nf dat a sckout sckin convert adum1402c out gnd in adr391 02969-048 figure 47 . a true 16 - bit isolated simultaneous sampling acquisition system rev. c | page 24 of 28
data sheet ad7686 outline dimensions c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 fig ure 48 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min figure 49 . 10 - lead lead frame chip scale package [ lfcsp_wd ] 3 mm 3 mm body, very thin, dual lead (cp - 10 - 9) dime nsions shown in millimeters rev. c | page 25 of 28
ad7686 data sheet rev. c | page 26 of 28 ordering guide model 1, 2, 3 integral nonlinearity temperature range ordering quantity package description package option branding ad7686bcpzrl 3 lsb max ?40c to +85c reel, 5000 10-lead lfcsp_wd cp-10-9 c02# ad7686bcpzrl7 3 lsb max ?40c to +85c reel, 1500 10-lead lfcsp_wd cp-10-9 c02# ad7686brmz 3 lsb max ?40c to +85c tube, 50 10-lead msop rm-10 c3n AD7686BRMZRL7 3 lsb max ?40c to +85c reel, 1000 10-lead msop rm-10 c3n ad7686ccpzrl 2 lsb max ?40c to +85c reel, 5000 10-lead lfcsp_wd cp-10-9 c2g# ad7686ccpzrl7 2 lsb max ?40c to +85c reel, 1500 10-lead lfcsp_wd cp-10-9 c2g# ad7686crmz 2 lsb max ?40c to +85c tube, 50 10-lead msop rm-10 c3p ad7686crmzrl7 2 lsb max ?40c to +85c reel, 1000 10-lead msop rm-10 c3p eval-ad7686sdz evaluation board eval-sdp-cb1z controller board 1 z = rohs compliant part, # denotes rohs co mpliant product may be top or bottom marked. 2 the eval-ad786sdz can be used as a standalone evaluation board or in conjunction with the eval-sdp-cb1z for evaluation and/or demonstration purposes. 3 the eval-sdp-cb1z allows a pc to control and communicate with all analog devices, inc. evaluation boards ending in the sdz designator.
data sheet ad7686 notes rev. c | page 27 of 28
ad7686 data sheet notes ? 2005 C 2014 analog devices, inc. all rights reserved . trademarks and registered trademarks are the property of their respective owners. d02969 - 0 - 8/14(c) rev. c | page 28 of 28

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